InstLatX64
@instlatx64.bsky.social
x86/x64, SIMD, #AVX512, "Aha!" moments. I have been writing code since 1986. Budapest, Europe https://instlatx64.github.io/InstLatx64/
#Intel released the SDE 10.13.1 (Software Development Emulator) with x86 EAG #ACE (Al Compute Extensions) support: www.intel.com/content/www/... #NovaLake #DiamondRapids #APX #AVX10_2
InstLatX64@instlatx64.bsky.social · 4mo ago#Intel released the SDE 10.8 (Software Development Emulator): www.intel.com/content/www/... #NovaLake #DiamondRapids #APX #AVX10_2
#AMD [1]: - #Zen8 EPYC: Ravenna - #Zen7 EPYC: -- for AI host Ferrara -- for Agentic Sandbox Fidenza - #Zen6 [2], [3]: -- desktop #OlympicRidge B80F80 #AM5 -- mobile #Medusa1 B80F00 AM5/FP10 -- mobile #Medusa2 BE0F00 #FP10 #Intel - #GriffinCove for RZL [4] - #CopperShark [5] - #ThunderHawk [6] 1/3
InstLatX64@instlatx64.bsky.social · last wk.InstLatX64 refresh: #Intel: - 2C+4c #Core 7 350, Core 5 320 #WildcatLake D0651 CPUID dump GitHub: github.com/InstLatx64/I...
docs.amd.com has now officially revealed that - #Medusa1 is FP10/AM5 - #Medusa2 is FP10 - #OlympicRidge is AM5 #Zen6 #Zen6c docs.amd.com/search/all?c...
InstLatX64@instlatx64.bsky.social · 5d ago#AMD -- desktop #OlympicRidge CPUID is B80F80 -- mobile #Medusa2 CPUID is BE0F00 lore.kernel.org/platform-dri...
Unfortunately, the Perfmon counters of the #Intel #NovaLake INT cluster inherited the grouped nature from the older *Coves with a central scheduler, so the number of ports used here is unknown (except for the 3 JEUs).
InstLatX64@instlatx64.bsky.social · 3w ago#Intel perf tool got #NovaLake CPUID 300F10 300F30 support: According to this commit, while the #ArcticWolf config is quite similar to #Skymont / #Darkmont (8 INT+4 FP, FP probably 128b->256b), the #CoyoteCove FP has increased to 6 ports from 4 in #LionCove / #CougarCove. github.com/intel/perfmo...
A new feature was mentioned for #Intel #CoralRapids on the Linux kernel mailing list: APIC timer virtualization lore.kernel.org/lkml/amnPFlS...
InstLatX64@instlatx64.bsky.social · last mo.InstLatX64 refresh: #AMD: - #MustangPeak #Zen6 #Threadripper [1] - #Zen7 #GrimlockPoint #GrimlockRidge #GrimlockHalo [2] - #Zen7 #EPYC #Florence [2] #Intel - #PantherLakeR E0652 [3] - #DiamondRapids 18A-P, HTT Off - #CoralRapids #Hygon - 900F80 Suzhou [4] GitHub: github.com/InstLatx64/I... 1/2
#AMD -- desktop #OlympicRidge CPUID is B80F80 -- mobile #Medusa2 CPUID is BE0F00 lore.kernel.org/platform-dri...
InstLatX64@instlatx64.bsky.social · 2mo agoThese pages reveal some details about the #AMD #Zen6-based #ThreadripperPro: CPUID BA0F80, #MustangPeak codename, #TR6 socket, TSMC 2-nm cores with DDR5 and PCIe Gen 6 support docs.amd.com/v/u/en-US/ug... docs.amd.com/v/u/en-US/ug...
#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 1-5" 40332 to 4.10, all-in-one: Vol1 24592-Rev. 3.25-May 2026 Vol2 24593-Rev. 3.45-Jul 2026 Vol3 24594-Rev. 3.38-Jul 2026 Vol4 26568-Rev. 3.27-Jul 2026 Vol5 26569-Rev. 3.16-Nov 2021 docs.amd.com/v/u/en-US/40...
InstLatX64@instlatx64.bsky.social · 5mo ago#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 1-5" 40332 to 4.09, all-in-one: Vol1 24592-Rev. 3.24-Aug 2025 Vol2 24593-Rev. 3.44-Mar 2026 Vol3 24594-Rev. 3.37-Jul 2025 Vol4 26568-Rev. 3.26-Jan 2026 Vol5 26569-Rev. 3.16-Nov 2021 docs.amd.com/v/u/en-US/40...
InstLatX64 refresh: #Intel: - 2C+4c #Core 7 350, Core 5 320 #WildcatLake D0651 CPUID dump GitHub: github.com/InstLatx64/I...
github.com
InstLatX64@instlatx64.bsky.social · 3w agoInstLatX64 refresh: #Intel - #WildCatLake D0651 [1] - #ClearwaterForest D06D1 [2] - #Xeon 658X 24-Core #GraniteRapids A06D1 CPUID dump - Xeon 6315P #RaptorLake B0671 CPUID dump GitHub: github.com/InstLatx64/I... 1/2
Until the 84-core #AMD #Sorano #EPYC 8635P came to mind (12 CCD x 7-core), this 176-core (8 CCD x 22-core) #Zen6c seemed completely incomprehensible without a 3rd CCD type. But supposing 11x3 core within the #Monarch CCD makes this a yield optimization. blogs.microsoft.com/blog/2026/07...
InstLatX64@instlatx64.bsky.social · 3mo agoThis SPEC pdf mentions two #AMD #Sorano #EPYC 8xx5 SKUs: AMD EPYC 8635P AMD EPYC 8225P www.spec.org/sert2/ISO_Re... 8635P seems the 84-core TOP SKU: www.connection.com/product/hpe-...
InstLatX64 refresh: #Intel - #WildCatLake D0651 [1] - #ClearwaterForest D06D1 [2] - #Xeon 658X 24-Core #GraniteRapids A06D1 CPUID dump - Xeon 6315P #RaptorLake B0671 CPUID dump GitHub: github.com/InstLatx64/I... 1/2
24-Core Intel Xeon 658X (Granite Rapids-SP) A06D1 CPUID dump · InstLatx64/InstLatx64@ae88464
-- 24-Core Intel Xeon 658X (Granite Rapids-SP) A06D1 CPUID dump added -- QuadCore Intel Xeon 6315P (Raptor Lake-S) B0671 CPUID dump added -- Intel Wildcat Lake full CPUID is D0651 [1] -- Intel Clea...
github.com
InstLatX64@instlatx64.bsky.social · last mo.InstLatX64 refresh: #AMD: - #MustangPeak #Zen6 #Threadripper [1] - #Zen7 #GrimlockPoint #GrimlockRidge #GrimlockHalo [2] - #Zen7 #EPYC #Florence [2] #Intel - #PantherLakeR E0652 [3] - #DiamondRapids 18A-P, HTT Off - #CoralRapids #Hygon - 900F80 Suzhou [4] GitHub: github.com/InstLatx64/I... 1/2
#Intel XED got #ACE (AI Compute Extensions) of x86 Ecosystem Advisory Group support: github.com/intelxed/xed... #ACE specification: x86ecosystem.org/wp-content/u... #ACE1 #AVX10_V2_AUX
InstLatX64@instlatx64.bsky.social · 8mo ago#Intel #XED commit, sync with 60th ISA Ext guide: #NovaLake (#CoyoteCove + #ArcticWolf) supports #AVX10_1 #AVX10_2 #APX #MOVRS #SM4 github.com/intelxed/xed...
CPUID.1Ah.EAX: 20000000: #Tremont 20000001: #Gracemont 20000002: #Crestmont 20000003: #Skymont 20000004: #Darkmont 20000005: #ArcticWolf 40000000: #SunnyCove 40000001: #GoldenCove 40000002: #RedwoodCove 40000003: #LionCove 40000004: #CougarCove 40000005: #CoyoteCove GitHub github.com/intel/perfmo...
InstLatX64@instlatx64.bsky.social · last yr.#Intel perfmon updated with #PantherLake CPUID.1Ah.EAX values: 20000000 #Tremont 20000001 #Gracemont 20000002 #Crestmont 20000003 #Skymont 20000004 #Darkmont 40000000 #SunnyCove 40000001 #GoldenCove 40000002 #RedwoodCove 40000003 #LionCove 40000004 #CougarCove github.com/intel/perfmo...
#Intel perf tool got #NovaLake CPUID 300F10 300F30 support: According to this commit, while the #ArcticWolf config is quite similar to #Skymont / #Darkmont (8 INT+4 FP, FP probably 128b->256b), the #CoyoteCove FP has increased to 6 ports from 4 in #LionCove / #CougarCove. github.com/intel/perfmo...
InstLatX64@instlatx64.bsky.social · 12mo ago#Intel #PantherLake got perfmon support: github.com/intel/perfmo... According to this #CougarCove and #Darkmont is similar to #LionCove and #Skymont, just the front-end/branch prediction is different.
Another interesting GCC patch: disabling the memory-form of NDD #Intel #APX instructions. #DiamondRapids is not mentioned, perhaps this is an #ArcticWolf related issue? i386: Add tuning to disable memory-form NDD gcc.gnu.org/git/?p=gcc.g...
InstLatX64@instlatx64.bsky.social · last mo.An interesting #APX GCC patch: i386: Disable SETcc.ZU generation on DMR/NVL via tune flag gcc.gnu.org/git/?p=gcc.g... Strange, isn't a 6 byte EVEX better than a 2/3/4 byte XOR + 3/4 byte SETcc? #DiamondRapids #NovaLake #PantherCove
#AMD refreshed the "AMD64 Flexible Return and Event Delivery (FRED) Virtualization" 69191 to v1.10 pdf: docs.amd.com/v/u/en-US/69... #FRED #Zen6 #Venice #Verano
InstLatX64@instlatx64.bsky.social · 6mo ago#AMD released the "AMD64 Flexible Return and Event Delivery (FRED) Virtualization" 69191 v1.00 pdf for #Zen6: docs.amd.com/v/u/en-US/69...
An interesting #APX GCC patch: i386: Disable SETcc.ZU generation on DMR/NVL via tune flag gcc.gnu.org/git/?p=gcc.g... Strange, isn't a 6 byte EVEX better than a 2/3/4 byte XOR + 3/4 byte SETcc? #DiamondRapids #NovaLake #PantherCove
InstLatX64@instlatx64.bsky.social · 4mo ago#Intel released the SDE 10.8 (Software Development Emulator): www.intel.com/content/www/... #NovaLake #DiamondRapids #APX #AVX10_2
According to this Linux kernel patch, the #AMD LP-core is clearly marked in the CPUID: CPUID.80000026h.EBX[31:28]=2 #Zen6LP lore.kernel.org/linux-acpi/2...
InstLatX64@instlatx64.bsky.social · 2mo agoThese pages reveal some details about the #AMD #Zen6-based #ThreadripperPro: CPUID BA0F80, #MustangPeak codename, #TR6 socket, TSMC 2-nm cores with DDR5 and PCIe Gen 6 support docs.amd.com/v/u/en-US/ug... docs.amd.com/v/u/en-US/ug...
InstLatX64 refresh: #AMD: - #MustangPeak #Zen6 #Threadripper [1] - #Zen7 #GrimlockPoint #GrimlockRidge #GrimlockHalo [2] - #Zen7 #EPYC #Florence [2] #Intel - #PantherLakeR E0652 [3] - #DiamondRapids 18A-P, HTT Off - #CoralRapids #Hygon - 900F80 Suzhou [4] GitHub: github.com/InstLatx64/I... 1/2
AMD Mustang Peak (Zen6 Threadripper) CPUID is BA0F80 · InstLatx64/InstLatx64@f2711d4
-- AMD Mustang Peak CPUID is BA0F80 (Zen6 Threadripper, TR6 socket), codename added [1] -- AMD Zen7 Grimlock Point, Grimlock Ridge, Grimlock Halo codenames added [2] -- AMD Zen7 EPYC codename is Fl...
github.com
InstLatX64@instlatx64.bsky.social · 3mo ago#Intel #PantherLakeR CPUID E0650: lore.kernel.org/lkml/2026051... GitHub: github.com/InstLatx64/I... github.com/InstLatx64/I...
#Intel released the 62nd edition of the ISA Extensions Reference with. #UTMR and #AMX_TF32 support removed (it means only one instruction: TMMULTF32PS) Download: cdrdv2-public.intel.com/922690/31943... #DiamondRapids #NovaLake #PantherCove #CoyoteCove #ArcticWolf
InstLatX64@instlatx64.bsky.social · 5mo ago#Intel released the 61st edition of the ISA Extensions Reference with PerfMon Masking and clarifications. Download: cdrdv2-public.intel.com/915637/31943... #DiamondRapids #NovaLake #WildcatLake #PantherCove #CoyoteCove #ArcticWolf CPUID.07h.01.EDX[22]= #SEC_TEE_ATTESTATION
This GCC patch reveals that the #Hygon CPUID 900F80 is Suzhou, and supports #AVX512 up to #AVX512_VP2INTERSECT (= #AMD #Zen5 level) github.com/gcc-mirror/g...
InstLatX64@instlatx64.bsky.social · 3mo agoThis GCC patch reveals some #Hygon CPUIDs, ISA levels, and codenames: github.com/gcc-mirror/g... - 900F40 Dharma #AVX2 - 900F60 Shanghai #AVX2 - 900F70 Chengdu #AVX512
I was wrong. According to this #AMD #Venice patch, #Zen6 's VNNI_INT8 capabilities are also supposedly better than #Zen5 's. github.com/amd/aocl-dlp...
InstLatX64@instlatx64.bsky.social · 9mo agoI think the "more AI pipelines" on #AMD #Zen6 means that ADD/SUB/MIN/MAX/CVT uops of "New AI Datatype"(=FP16) can go into FP23 ports also, against the FP01-bounded #AVX512_VNNI / #AVX_VNNI uops.
Visualized #AMD #Zen5 #ThreadripperPro 9000WX topology: www.instagram.com/p/DZ31Gu_FwT... www.instagram.com/p/DZ31Gu_FwT... On AMD.com : www.amd.com/en/products/...
InstLatX64@instlatx64.bsky.social · 2mo agoThese pages reveal some details about the #AMD #Zen6-based #ThreadripperPro: CPUID BA0F80, #MustangPeak codename, #TR6 socket, TSMC 2-nm cores with DDR5 and PCIe Gen 6 support docs.amd.com/v/u/en-US/ug... docs.amd.com/v/u/en-US/ug...
#Intel released the 92nd edition of the Software Developer’s Manuals with fixes and clarifications: All-in-One: cdrdv2-public.intel.com/922475/32546... Changes v084: cdrdv2-public.intel.com/922474/25204...
InstLatX64@instlatx64.bsky.social · 4mo ago#Intel re-released the 91st edition of the Software Developer’s Manuals with minor fixes: cdrdv2-public.intel.com/916575/32546...
Strange. #AMD's documentation page lists both #SP7 and #SP8 's embedded #Zen6 #EPYC as 9006 instead of 11006/10006 (or B006/A006 if they've switched to the more practical hex notation). docs.amd.com/search/all?v...
InstLatX64@instlatx64.bsky.social · last yr.New #Intel CPUIDs [1]: - #NovaLake 300F10 (Family 18 model 1) - #NovaLakeL 300F30 (Family 18 model 3) New dump: -Core Ultra 9 275HX C0662 #ArrowLakeHX New #AMD #Zen6 Venice #EPYC socket assignments [2]: -B50F00, BC0F00 #SP7 16 m. c. -B90F00, BA0F00 #SP8 8 m. c. GitHub: github.com/InstLatx64/I... 1/2
