Looking back on our Fremont 2026 Summer Internship Program. Here’s what this year’s class had to say about their experience. ⬇️

What comes after gate-all-around? Our Semiverse® Solutions team modeled a self-aligned CFET architecture that cuts SRAM bit cell area by 52.7% versus N3. It’s a path for scaling beyond 10 Å. https://bit.ly/4yBBdXd

Before a single film is deposited or a single feature is etched, there needs to be a foundation. This week’s Word of the Week is the material that provides the physical, electrical, and thermal groundwork for every semiconductor device. Watch below to reveal the word.

Explore the cutting-edge tools tackling advanced packaging’s most challenging hurdles, from microbump uniformity to void-free plating and more. ⬇️ https://bit.ly/3L2qilH

What do you call the complete process of making a semiconductor chip? 🤔 There’s a two-word answer for everything from building devices and wiring to assembling, packaging, and testing. Find the answer below.

Lam Research opened its largest U.S. warehouse in Livermore, CA: 470+ sq. ft., 15 robots, part retrieval in under 30 seconds. Eight CA facilities consolidated into one hub, built for AI era semiconductor demand. https://bit.ly/4e76etJ

As 2 nm chips continue production, new possibilities for performance and efficiency across computing are coming into focus. See where 2 nm could make the biggest impact and read the blog post for more. https://bit.ly/4rdcULx

Advanced packaging pop quiz! Do you know this one? Take your best guess, then follow the video below for the answer!

In today’s edition of Movie Monday, explore the industry’s shift from wafer-level packaging (WLP) to panel-level processing (PLP), the technical challenges ahead, and why collaboration across the semiconductor ecosystem is key to accelerating adoption. bit.ly/4xN1twI

If one lane is wider than the others on a highway, more cars naturally shift into it. 🚗 Similar imbalances can happen inside GAA transistors, where uneven stress causes one channel to carry more current than others. See how SEMulator3D® helps spot these before fabrication. https://bit.ly/3VhZu5J

Great pitchers know it’s all about the changeup. Syndion®’s rapidly alternating process moves between etch and deposition steps to carve deep, high aspect ratio features with precise depth uniformity. See the play-by-play. https://bit.ly/4AhLvNp

What stores data using magnetism instead of electric charges? 🧲 Take your best guess, then watch to reveal the correct answer.

🆘The challenge: As 3D NAND stacks grow taller, increasing film stress can cause wafer bowing. ✅ The solution: Techniques like carbon plugs and stress compensation help manage these challenges. More here: https://bit.ly/4x1GDJC

Watch the video to see how SABRE® 3D enables the next generation of advanced packaging and tap the link to learn more via our blog. bit.ly/4h6Gz5d

How well do you know our advanced packaging tools? 🤔 Let’s find out! Watch below to make your pick and see if you got it right.

In semiconductor manufacturing, removing one material faster than another requires precision. What term best describes their removal rates? Find out below!

Greater experimentation. Closer collaboration with customers. Faster development of advanced AI chips. That’s what our new R&D lab in Tualatin will do. During the groundbreaking, we also donated $50K to the Tualatin Food Pantry in support of our community. A few moments from the day with us. ⬇️

Fine-pitch hybrid bonding works. Scaling it is different. Lam’s Erik Edelberg: “HVM is all about high-volume, wafer-to-wafer consistency and across-wafer consistency.” Semiconductor Engineering breaks down what the path to production actually requires. https://bit.ly/4zQoD7s

Behind the scenes with Ankita, one of our materials engineering interns. Take a look!

How do hundreds of individual manufacturing steps come together to fabricate a device on a wafer? Manufacturers perform each process in a specific order to build the device step by step. Do you know the term?

We broke ground on a new lab facility in Tualatin, OR, expanding cleanroom capacity by 50%. Part of a $3B+ global lab investment to compress the path from materials discovery to production-ready chips in the AI era. https://bit.ly/3UQAVN3

What is advanced packaging? It’s how multiple chips come together in a single package to enable smaller, higher-performing chips for AI. See how we help make it possible: https://bit.ly/4za72XU

A summer at Lam looks like this with central lab operations intern Joelle Iyasele.

Lam Research broke ground today, introducing the new 120k sq ft lab in Tualatin, OR, as part of a $3B+ planned global lab investment. The lab is expected to expand cleanroom capacity by 50% and accelerate chip innovation for the AI era. Learn more. https://bit.ly/45Qq4Fi

Imagine taking 800 shots at a target, but less than 10% hit the bullseye. Chipmakers face a similar challenge at the N3 node, where metal pitch dimensions must be at or below 18 nm. Here's how SEMulator3D® found significant process parameters for successful EPE control. 🎯 https://bit.ly/4i16fjV

Mask costs don't stop leading edge scaling. They shape how it happens. Hear from our VP Rich Wise as he joins Semi Engineering to weigh in on what high-NA EUV demands from chipmakers in resist, etch, and materials. https://bit.ly/45Xe5Wl

A day in the life, one photo at a time. 📸 See what your internship at Lam could look like.

Kiyo® is up to bat. ⚾ See what this product family brings to semiconductor manufacturing. https://bit.ly/4xcVQZ8

Our global R&D networks: 3 regions, 24/7 operations, 1M+ experiments annually, and process development up to 2.5x faster. Learn more about Lam's global labs strategy: https://bit.ly/3Se8rvV

Recipe #1, #2, or #3? Put your virtual fabrication knowledge to the test below and then read the blog post to reveal the answer. https://bit.ly/3ZmIFWd