Logic Destroyer — Proven in Silicon.

@logicdestroyer.bsky.social

I breed Linux ASICs.

#FPGA #RISCV Reinventing the wheel, I wrote a frugal 32b/64b RISC-V compliant div/rem, early out, nonrestoring radix-2 divider. * 32b: 640 MHz, 155 LUTs, 14-36 cycles * 64b: 520 MHz, 289 LUTs, 22-68 cycles (UltraScale+ -1 fabric) Per Jan's Razor, planning to share one div/rem unit per 2-4 PEs.

Vivado device view of a critical path in a fast frugal 32b divider.