Had a great Igalia week last week, @lukel97.bsky.social, Cathie and I fed other Igalians some Zongzi, told them the story of the Dragon Boat Festival and taught them how to write Chinese words related to the festival! (Forgot to take a picture of our table but I have a picture of preps ^^)
I've been working for a long time alongside different folks to spread the word about web standards, how JavaScript is standardized and help improve how responsive we are to the needs of developers. For more @tc39.es lore, read my first post in "What even is Ecma?" www.ryzokuken.dev/blog/about-e...
What even is Ecma? (Part 1)
Ujjwal Sharma — Developer Advocate at Igalia, TC39 Co-chair, ECMA-402 Co-editor.
ryzokuken.dev
One of the nice parts of #llvm is that often times you'll find yourself needing to do some sort of non-trivial analysis, but usually there's already a pass for it. Here's how you can reuse a block frequency analysis to make a chess engine 7% faster on #riscv: lukelau.me/2026/01/26/c...
Closing the gap, part 2: Probability and profitability
Welcome back to the second post in this series looking at how we can improve the performance of RISC-V code from LLVM.
lukelau.me
Does LLVM produce slower RISC-V code than GCC? Currently, yes. Can we make LLVM produce faster code? Also, yes! lukelau.me/2025/12/10/c... #llvm #riscv
Closing the LLVM RISC-V gap to GCC, part 1
At the time of writing, GCC beats Clang on several SPEC CPU 2017 benchmarks on RISC-V1: Compiled with -march=rva22u64_v -O3 -flto, running the train ↩
lukelau.me
"How NOT To Program an Out-of-order Vector Processor" slides are public. static.sched.com/hosted_files...
We're looking forward to the RISC-V Summit North America next week where Mikhail Gadelha (one of our compiler engineers) will be presenting "Unlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-V". Be sure to catch his talk next Thurs riscvsummit2025.sched.com/event/28OTp/...
Police have deployed an armoured vehicle in Hong Kong's commercial heart, amidst an ongoing heavy security presence on the 36th anniversary of the Tiananmen Square crackdown. In full: buff.ly/f4hVB50
In Pictures: HK police deploy armoured vehicle on Tiananmen anniversary
Police have deployed an armoured vehicle in Hong Kong's commercial heart, amidst an ongoing heavy security presence on the 36th anniversary of the Tiananmen Square crackdown.
buff.ly
I'm delighted to see two of @igalia.com's projects for RISE highlighted at the RISC-V Summit Europe. Find out more about our work on both LLVM optimisation and testing/CI on the RISE blog (with more to come in the future!): riseproject.dev/2025/05/08/p... riseproject.dev/2024/10/15/w...
We're looking forward to EuroLLVM next week in Berlin. Be sure to check out talks from my colleague @lukel97.bsky.social and myself on: * Work to further improve RISC-V vector codegen (extending the VL Optimizer), and * Work done with the support of RISE to improve RISC-V LLVM testing.
Igalia@igalia.com · last yr.We’ll be at #EuroLLVM 2025 in Berlin next week with talks from @asbradbury.org and Luke Lau!
What if I told you 3DNow! square root recíprocals are defined for negative numbers?... Also the amazing FEX 2503 is out. Read about some of my work and the work of other FEX maintainers' in the release notes: fex-emu.com/FEX-2503/ #fex #igalia #gaming #linux #arm64
FEX 2503 Tagged
Here we are again, another month and some more cool changes with FEX. Let’s dive in and see what has changed!
fex-emu.com
Some notes on ccache+LLVM. Summary: if you do a lot of builds across different checkouts/worktrees/builddirs, be sure to set the base_dir option and -DLLVM_USE_RELATIVE_PATHS_IN_DEBUG_INFO=ON muxup.com/2025q1/ccach...
ccache for LLVM builds across multiple directories
TL;DR: ccache base_dir saves the day
muxup.com
Hello you fine Internet folks, Today's article is on SiFive's P550 microarchitecture. The P550 core is one of the fastest RISC-V cores available currently and is claimed to be comparable to ARM's Cortex A75. Hope y'all enjoy! old.chipsandcheese.com/2025/01/26/i... open.substack.com/pub/chipsand...
Inside SiFive’s P550 Microarchitecture
RISC-V is a relatively young and open source instruction set. So far, it has gained traction in microcontrollers and academic applications. For example, Nvidia replaced the Falcon microcontrollers …
old.chipsandcheese.com
New blog post covering the mysterious 10ms startup regression of Node.js on macOS, the journey of investigating the issue with various performance tools, and figuring out the fix (which also helped making the binary smaller). joyeecheung.github.io/blog/2025/01...
Executable loading and startup performance on macOS
Recently, I fixed a startup performance regression in Node.js on macOS after an extensive investigation. Along the way, I learned a lot about tools on macOS and Node.js compilation workflows that don’
joyeecheung.github.io
After two months of chasing, finally found out what's happening behind this mysterious startup time regression on macOS from Node.js v20.x - it's missing -fvisibility=hidden 😅 (I guess that's what happens when the build configs become dusty enough) github.com/nodejs/node/...
build: build v8 with -fvisibility=hidden on macOS by joyeecheung · Pull Request #56275 · nodejs/node
V8 should be built with -fvisibility=hidden, otherwise the resulting binary would contain unnecessary symbols. In particular, on macOS, this leads to 5000+ weak symbols resolved at runtime, leading...
github.com
Recently I came across this treatise by Stephen Dolan github.com/ocaml/ocaml/...
Abnormally slow loop (25x) under OCaml 5 / macOS / arm64 · Issue #13262 · ocaml/ocaml
Hello, I am using macOS Ventura 13.6.7 with an Apple M2 Max processor. A loop that writes values into an integer array is about 20x slower with OCaml 5 than with OCaml 4. Using Array.set versus Arr...
github.com
Trying to find the slowest possible RISC-V instruction. This single vlse8.v with a stride of 65536 bytes takes 66 million cycles on a Banana Pi F3. That's 0.04 seconds @1.6GHz #risc-v
