Runs WireGuard at full speed directly on an inexpensive Artix7 FPGA using entirely open-source tools without requiring a PC host or proprietary IP blocks.

Pypeline HDL makes verification as easy as Python. See ChaCha20-Poly1305 cryptography blocks in the Chili.CHIPS WireGuard FPGA design: github.com/JulianKemmerer/PipelineC/blob/master/examples/pypeline/chacha20poly1305/pypeline_sim_and_wireguard.md #hardware #fpga #rtl #hls #eda

Introducing Pypeline(HDL): new Python front end for PipelineC Very experimental, see: LLM assisted, but nonetheless seems to be working so far and I am excited. There are some generated docs here for basic overview stuff: github.com/JulianKemmer... and I am happy to answer questions too 🤓

A SoC in C? StreamSoC shows how to move from embedded C software to custom PipelineC hardware for doing things like realtime streaming data processing. youtu.be/dzF3okigyog

A SoC (System on Chip) in C? StreamSoC FPGA real-time audio video project

YouTube video by PipelineC

youtu.be

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions. github.com/JulianKemmer... #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources. github.com/JulianKemmer... #rtl #hls #verilog #vhdl #asic #eda

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 4: video-like stream of 'pixel' data to a sliding 3x3 window via line buffer fifos. Auto pipeline for kernel function (counting neighbors), ~150M windows per sec. github.com/JulianKemmer... #fpga #rtl #hdl #hls #aoc25

Advent of Code Day 9: Iterates over RAM holding points. Autopipeline computes N rectangle areas per clock cycle and finds max. Easily does N=4 at ~100MHz with few pipeline stages, ~400M rect areas computed per sec 🎄 github.com/JulianKemmer... #fpga #rtl #hdl #hls #aoc25

Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz. ~1 Gbyte per sec of ascii could be processed 😎 🎄 github.com/JulianKemmer... #aoc25 #fpga #hdl #hls

Advent of Code 2025 Day 2 in FPGA 🤓 github.com/JulianKemmer... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

"How do FPGAs execute blocking assignments in one clock cycle?" Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL. www.reddit.com/r/FPGA/comme... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

How to send a struct from one dev board to another? A PipelineC Story #hdl #hls #RTL #fpga #ethernet #i2s #hardware www.reddit.com/r/FPGA/comme...

From the FPGA community on Reddit: How to send a struct from one dev board to another?

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implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA glasgow-embedded.org/latest/apple...

#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing". insidehpc.com/2025/04/jaso... C-to-gates was a dream until Cong made it real.

Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL ! #dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...

What can you do with reading arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes), write a little #python script that launches #GTKWave, and you have a tiny homemade cross platform logic analyzer thing! github.com/JulianKemmer...

#hardware debugging and wanted to see some #ethernet MAC address registers down in my pico-ice #ice40 #fpga design. Don't want manufacturer specific ILAs. Don't want to route signals to top, external #debug equipment I don't have. Just assign to #UART debug probe wire: github.com/JulianKemmer...

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying so I have revived the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and will demo that on the pico ice

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi@mastodon.radio! #embedded #HDL #RTL #Verilog #VHDL #HLS github.com/JulianKemmer...

👋 Hi, I’m Max! Principal Engineer @ Intel & lead of ROHD, an open-source project making hardware design more fun & accessible. Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech! #introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD

I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits. Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...

Ken Shirriff@righto.com · 2y ago

Adding on a computer is trickier than you'd expect. The Pentium processor (1993) used a variety of circuits for addition. I reverse-engineered an adder in the floating point unit and found that it is a "Kogge-Stone carry-lookahead adder", using some tricks to make it faster. Let's look inside. 1/n

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @raspberrypi.com. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

In the mood for the littlest bit of #FPGA #GameDev? 🤓 Check out this pico-ice based pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 github.com/JulianKemmer...

Gifted a new #FPGA dev board this season? 🤓 PipelineC aims to make #hardware description easier for #embedded folks. Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #hls github.com/JulianKemmer...

Dev Board Setup

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC

github.com

Part of why FPGAs are amazing is getting to be part of this hard 💪 hardware world while getting a relatively faster recompile and test cycle like software. I♥️#FPGA

Matt Venn@mattvenn.net · 2y ago

It’s become a cliche, but hardware is hard! One reason why hardware is harder than software is that the time between revisions is often longer. We need to wait for new PCBs, or for components to be delivered. Or for more new PCBs after we realise we got it wrong!