Semiconductor Engineering
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Deep insights for the chip industry. semiengineering.com Hot topics: semiconductor, EDA, advanced packaging, hardware, low power, HPC, hardware security, automotive chips, embedded, edge computing, semiconductor manufacturing, chip design, VLSI
Chip Industry Week In Review semiengineering.com/chip-industr...
Chip Industry Week In Review
2D Tunnel FET; in-memory photonic computing; India's $13.4B Semicon 2.0; SEMICON Taiwan; PCIe 6/7 test; MediaTek deal; 300mm Si photonics; InP expansion; $75M to recycle rare earths; GF PDKs; Gain-Cel...
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The common denominator for all kinds of robots is a heterogeneous architecture comprised of MCUs, MPUs, CPUs, GPUs, image signal processing, and digital signal processing. semiengineering.com/humanoid-com...
Humanoid Compute, Security More Complex Than AVs
Robots and autonomous vehicles are both edge devices, but a humanoid has wheels as well as fingers. Close interaction with humans raises the stakes.
semiengineering.com
The imec Report: Advancing The CFET-Based Device Roadmap semiengineering.com/advancing-th... #cfets #semiconductor
The imec Report: Advancing The CFET-Based Device Roadmap
Part I: Novel integration modules and standard cell configurations.
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From Spec To Formal Properties semiengineering.com/from-spec-to... #verification #VLSI #EDA #semiconductor
From Spec To Formal Properties
Can LLMs turn a specification into a set of formal properties that can be used to verify an implementation? The answer is getting closer to being yes, but with caveats.
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Optical chiplets promise a way out of the bandwidth, power, and reach limits of copper interconnects, but bringing photonics into advanced packages is proving more difficult than just swapping one signaling medium for another. semiengineering.com/photonics-fo... #photonics
Photonics Forces A Chiplet Rethink
Thermal drift, stress, electromagnetic coupling, and verification gaps are turning optical integration into a full-system co-design problem rather than a plug-in bandwidth upgrade.
semiengineering.com
Big week in the chip industry semiengineering.com/chip-industr... #semiconductor
Chip Industry Week in Review
Hot Chips AI HW wave; HBM vs HBC; capacity buildout; Infineon's latest buy; advanced packaging enablers; foundry report; ASIC security threats; IC tariffs; executive changes; Nvidia, Synopsys earnings...
semiengineering.com
Big week in the chip industry semiengineering.com/chip-industr... #semiconductor
Chip Industry Week in Review
Hot Chips AI HW wave; HBM vs HBC; capacity buildout; Infineon's latest buy; advanced packaging enablers; foundry report; ASIC security threats; IC tariffs; executive changes; Nvidia, Synopsys earnings...
semiengineering.com
Adding more layers requires thinning of memory dies in the stack in order to stay within the HBM package height limit. But thinning DRAM dies is reaching the breaking point — sometimes literally. semiengineering.com/issues-stack... #HBM
Issues Stack Up With More HBM Layers
Hot Chips 2026: Thinner dies, more TSV area, thermal dissipation, and limited manufacturing capacity make HBM scaling much more difficult.
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Data centers are gearing up for a future in which a single rack could consume as much power as an entire building. semiengineering.com/the-1-megawa... #datacenters
The 1-Megawatt Rack Debate
Is it better to cram more compute into each rack or rethink the architecture?
semiengineering.com
Special Report: Multi-Die Assemblies Dominate At 2nm And Below semiengineering.com/multi-die-as... #semiconductor
Multi-Die Assemblies Dominate At 2nm And Below
Chips are getting bigger, more modular, and much more capable as new innovations mix with existing processes and long-researched projects go mainstream.
semiengineering.com
Performance advantage may come down to material choices and precise interconnect decisions. semiengineering.com/cfets-forge-...
CFETs Forge Better Connections
Performance advantage may come down to material choices and precise interconnect decisions.
semiengineering.com
Latest news semiengineering.com/chip-industr... #semiconductor
Chip Industry Week In Review
New Micron lab; chip/AI price jump; multi-die monitoring; cryo links for quantum chips; interconnect RC bottleneck; 18A win; CPO roadmap; 2 new CEOs; humanoid readiness gap; Hot Interconnects.
semiengineering.com
Ultimately, where practical, cHBM is about differentiation. semiengineering.com/how-will-the... #HBM
How Will The Custom HBM Business Work?
There is no one-size-fits-all — yet.
semiengineering.com
The power issues facing AI data centers are spilling over onto individual dies, where engineers are working to minimize loss in the form of heat while maximizing the amount of power that makes it to the gates. semiengineering.com/800vdc-pushe...
800VDC Pushes AI Power Design From Grid To Gate
The next power bottleneck is no longer just inside the accelerator — it is the full conversion path from medium-voltage AC to sub-1V silicon.
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Earnings were strong across all chip industry sectors this quarter, with 11 companies posting triple-digit growth, and all but 2 of the 80 companies reported here were in positive territory. semiengineering.com/chip-industr... #semiconductor #earnings
Energy and thermal concerns are forcing more companies to create specialized solutions even during a time of rapid change. semiengineering.com/vertical-int... #semiconductor #EDA
Vertical Integration Becoming Pervasive
No system can be optimized without an understanding of both the hardware and software, and making the right architectural choice requires cooperation.
semiengineering.com
New technical papers recently added to Semiconductor Engineering’s library semiengineering.com/chip-industr... #semiconductor
Latest news in the semiconductor industry semiengineering.com/chip-industr... #semiconductor
Chip Industry Week In Review
Lam Research and ASE expansions; data center shifts; CPO system architecture initiative; 2D-transistor interface solution; USENIX HW security; patent suits; image sensors; programmable AI memtransistor; Nvidia's new plan; earnings; Tier IV's L4 auto chip.
semiengineering.com
Data-center network fabrics are undergoing another architectural shift as optical interconnects assume a larger role in AI-cluster connectivity, extending into scale-up domains and influencing overall topology design. semiengineering.com/coppers-grip... #optics #datacenters #interconnects
Copper’s Grip On AI Scaling Is Starting To Slip
As AI clusters push beyond rack-scale limits, optical interconnects and circuit switching are reshaping how data centers scale.
semiengineering.com
“CPO test will not scale if every product, supplier, package, optical interface, and test cell is treated as a custom engineering project." semiengineering.com/cpo-test-won...
CPO Test Won't Scale Without Standardization
Across the CPO ecosystem, profitability will not happen until standardization occurs.
semiengineering.com
Special Report: As HBMs grow in stack height and complexity, so does the testing approach and design-for-test strategy. semiengineering.com/hbm-becomes-... #HBM
HBM Becomes Testbed For 3D Assembly Yield
High-bandwidth memory has become a proving ground for 3D stack testing, DFT, and reliability.
semiengineering.com
The Next Big Chip Failure May Be A Security One: Semiconductor leaders say hardware trust, verification, and lifecycle resilience must become core design requirements rather than late-stage additions. semiengineering.com/the-next-big... #semiconductor #hardwaresecurity #softwaresecurity
A race is underway to develop reliable, fast, and secure communications networks, which are essential for transferring data between satellites, spacecraft, compute centers, autonomous mobile robots and rovers (AMRs), and astronauts. semiengineering.com/as-space-get...
As Space Gets Connected, Security Gets Critical
NASA is in the process of bringing terrestrial internet capabilities to astronauts, rovers, and orbiters, which means a network of high-value data will be up for grabs by ransomware actors or rogue na...
semiengineering.com
Latest news in the chip industry semiengineering.com/chip-industr... #semiconductor
Chip Industry Week in Review
SK hynix's $38B new fabs; memory density increases; 2026 chip industry revenue to hit $1.65T; imec metrology roadmap; MIT's self-assembled contacts; new U.S. restrictions; Intel's new training program...
semiengineering.com
Latest news in the chip industry semiengineering.com/chip-industr... #semiconductor
Chip Industry Week in Review
SK hynix's $38B new fabs; memory density increases; 2026 chip industry revenue to hit $1.65T; imec metrology roadmap; MIT's self-assembled contacts; new U.S. restrictions; Intel's new training program...
semiengineering.com
Security is no longer a separate discipline. It’s an integral part of every aspect of chip design through manufacturing and beyond that semiengineering.com/ai-friend-an... #semiconductor #AIsecurity
AI: Friend And Foe For Chip Security
AI has access to every known security paper and powerful tools, but that's not all bad.
semiengineering.com
The speed gains from leading-edge AI accelerators and multi-die architectures can be lost if on-chip networks are not optimized to handle diverse types of data traffic moving between memories and processors. semiengineering.com/untangling-c...
Untangling Chip Traffic Jams
Scaling NoCs across chiplets requires earlier validation of coherency, congestion, thermal effects, and fault behavior.
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How to achieve a 10X productivity improvement using AI agents. youtu.be/WMKiQUYQhnA?... #ASIC #AgenticAI #chipdesign
AI Agent Orchestration For ASIC Autonomy
YouTube video by Semiconductor Engineering
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Catch up on the latest news in the chip industry semiengineering.com/chip-industr... #semiconductor
Chip Industry Week In Review
DAC's big buzz; CHIPS Act $; China's immersion DUV; UMC expands; SIA's state of the industry; DRAM shortages; earnings; PCB design credential program; IBM's quantum advantage; AI security alliance; fo...
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