This should be the final production version of the DDR4 adapter board. Did a last minute revision to add reverse polarity protection to the 9 volt programming voltage connection. Prototypes are in production now, after a final test we'll make a small batch.

Automate your Bus Pirate with Rust programs using a crate that neatly abstracts the BPIO2 flatbuffer interface: github.com/DangerousPro...

A Python library for Bus Pirate automation. This simple wrapper for the BPIO2 FlatBuffers interface makes scripting easy. Includes examples for I2C, SPI, and 1-Wire protocols - and a SPI flash read/write demo. Much cleaner than raw FlatBuffers. tinyurl.com/ykxdpv7v

Control your Bus Pirate from PC software with the simple FlatBuffers interface. Flatc(c) provides premade tooling for a bunch of languages including C/++/#, Python, Rust, Go, Java, etc. Include the tooling in your app/script and skip the low level protocol stuff.

As of this morning the DDR5 adapter plank is on back order for about 2 weeks. You might be able to score one at a distributor (PiHut UK) earlier. The DDR4 plank I'm working on now should be in production just in time for a messy Spring Festival delay :)

DDR4 UDIMM (desktop style)RAM stick arrived for a final test of the adapter plank. The new Bus Pirate 'ddr4' command correctly identifies the module by reading the SPD data. I'm going to make a few tweaks to the adapter, and this should be the final production revision.

Big moment: will magic smoke escape? DDR4 wants 9 volts on address pin 0 before it allows changes to write protection. We're using a bench supply, to be replaced by a 9 V battery later. The High Voltage is applied when needed by an optocoupler and Bus Pirate pin.

Made a prototype adapter for reading/writing previous gen DDR4 RAM sticks. Dumping the contents via I2C is easy. We can tell that this is a DDR4 SODIMM made in 2018 by Kingston with Micron DRAM chips. S/N ACR24D4S7S8MB-4. There's some manuf. specific data too which may be extended profile info.

Ian, to your GPS resource, please consider adding the cross-platform, free, and open-source GPSBabel. CLI and GUI. Twenty four years & counting. It can reduce, interpolate, toss out junk, etc. Coming soon (merged to Git): Kalman filter www.gpsbabel.org Specfically www.gpsbabel.org/htmldoc-deve...

Anyone going to 39C3 in Hamburg this December? It's my first, and I hope we get a chance to meet up if you'll be there too!

New I2C quick connect adapter plank! One board to rule them all - supports Qwiic, Stemma (3P/4P/QT), Grove, Gravity, and Breakout Garden connectors. Quick prototyping with the Bus Pirate and your favorite solder-free ecosystem.

New tutorial: Learn NMEA GPS modules with the Bus Pirate! Connect any GPS module via UART, decode NMEA sentences in real-time, and extract coordinates/satellite data. Includes a full teardown of common NMEA sentences. docs.buspirate.com/docs/devices...

Time to upgrade a 10-year-old GPS! New modules track all 4 GNSS systems (GPS/BeiDuo/GLONASS/Galileo) for faster locks & better accuracy. Ublox NEO-M9N ($10) is common and solid, but the ZhongKeWei ATGM336H-F8N76 ($6.50) is cheaper with more frequencies/satellites. Any other recs?

The latest Bus Pirate firmware has a usbpd command to probe and trigger USB C power delivery. Select a fixed voltage profile, or specify a voltage if PPS is supported. We used a generic AP33772S breakout board for development, but a Bus Pirate USB PD plank prototype is in the works.

USB-C PD enables fast charging with fixed & programmable voltage outputs. Using Bus Pirate + AP33772S, I found charger labels don't always match actual PD profiles. This laptop charger lists 5/9/15/20V, but also supports 3.3-21V programmable output—unlabeled. More below..

DDR5 RAM Serial Presence Detect chips tell a computer about the RAM specs. It has 1024 bytes of EEPROM storage, temperature monitoring, and pass-through access to a Power Management IC (PMIC). I wrote a very hands on low-level demo on how to access the chip using a Bus Pirate

I love the expandability of the Bus Pirate. Fully open source with a great community, it's easy to add new functionality to interface to different hardware and busses.

Ian @ Dangerous Prototypes@buspirate.bsky.social · 10mo ago

It took 3 revisions to get right, but the DDR5 RAM SPD adapter is now available. Use with the Bus Pirate to read and write DDR5 SPD EEPROMs. HSA pin is grounded so blocks can be unlocked (offline mode). UDIMM (desktop) and SODIMM (laptop) supported.

It took 3 revisions to get right, but the DDR5 RAM SPD adapter is now available. Use with the Bus Pirate to read and write DDR5 SPD EEPROMs. HSA pin is grounded so blocks can be unlocked (offline mode). UDIMM (desktop) and SODIMM (laptop) supported.

Super happy with the new Bus Pirate HEX viewer! Valid ASCII and non-zero values are highlighted. Quiet mode (-q) hides addresses for easy paste into HEX editors. Dump range can be specified, and paging is enabled by default. Used in all data dump commands: DDR5 tool, SLE4442...

Grabbed some SHT3x and SHT4x temperature and humidity sensors for a Bus Pirate demo. SHT3x is a significant upgrade to the ancient SHT2x with a wider temperature and humidity range, and higher accuracy at the extremes. SHT4x slightly improves on the SHT3x specs, but is mostly...

The typical 8 pin memory chip has ground (GND, VSS) on pin 4 and power (VCC) pin 8. It doesn't appear to be a formal standard, but more a tradition. Modern EEPROMs (24x, 25x), flash (25Qx), SRAM (23x) and FRAM all have a similar power n ground pinout. However there are a couple oddities out there...

My #jumperless + #BusPirate all pimped out and ready to party! @buspirate.bsky.social @architeuthisflux.bsky.social

Has anyone used a Microchip UNI/O single wire EEPROM? Protocol looks like Manchester encoded I2C. Debuted >10 years ago (when 1-Wire was already a zombie) with talk of a bunch of devices. Today there's just a couple EEPROMs, and a few hits on GitHub. Single wire must kill it...

About twice a year I need a through hole resistor kit, but this is also fine... The Bus Pirate eeprom command is now read/write/dump/verify/testing 1-Wire EEPROMs.

The Bus Pirate I2C EEPROM command is coming along, so I wanted to see if we can use a common code base to work with SPI EEPROMs. I narrowed the list of SPI EEPROMs down to this set with common page sizes and addressing methods. Most SPI EEPROMs have write protection blocks...

Working on a command to dump, read, write, verify, erase and test I2C EEPROMs. Held off on doing this because there are so many EEPROM variations, but it should work with every 24XX EEPROM from Microchip (née ATMEL) and their major competitor, uh, also Microchip.

Picked up a handful of new breakouts recently, one was a FRAM chip. Ferroelectric RAM is a fairly new type of memory with the speed of SRAM and the persistence of EEPROM. It’s still much more expensive than EEPROM, flash or SRAM, but check out these benefits:

DDR5 UDIMM and SODIMM modules on a prototype breakout board. Motherboards detect DDR5 via a "SPD hub" chip with an I2C/I3C interface. A 128 byte register configures the hub and temperature sensor. Standard tables in a 1024 byte EEPROM describe how to configure the RAM.

Bus Pirate documentation update is complete! A new automated system captures and converts terminal output to screencasts and HTML to keep the docs up to date. Docusaurus is slow and v3 choked on a lot of Bus Pirate output, so we ported the whole site to super fast Hugo Docs.

RP2350 supports a second NOR flash or PSRAM. Trying PSRAM, but QSPI only sends 0xFF. Here it should send 0x9F and read 6 bytes to get the chip ID. Sending any value results in 0xFF on the bus. Not sure if this is a hardware or software issue.