POV: you've blamed the testbench, the tool, the PDK, and the moon. Day 1: "It worked in simulation." Day 2: "It's probably a timing issue." Day 3: "It's probably haunted." Day 4: it was the RTL.
Rohan makes ASICs 🛠️
@rohan-devarc.bsky.social
Exploring the ASIC lore. Not your typical lobste. rs link-dumper or book-cover–posting zombie.
The first tapeout i was a part of feels good to see it working 😁😁
Rohan makes ASICs 🛠️@rohan-devarc.bsky.social · last wk.We have the silicon. And it's working🎉🍾 ROM-less CORDIC engine hooked up to an SPI master @ 22 MHz. Thanks @tinytapeout.com We pulled it off! Cheers to @aksharvastarpara.bsky.social, Rohan Sundar, @deeempak.bsky.social, Praveen, Devang, Rishik, and Tejas.
We have the silicon. And it's working🎉🍾 ROM-less CORDIC engine hooked up to an SPI master @ 22 MHz. Thanks @tinytapeout.com We pulled it off! Cheers to @aksharvastarpara.bsky.social, Rohan Sundar, @deeempak.bsky.social, Praveen, Devang, Rishik, and Tejas.
Rohan makes ASICs 🛠️@rohan-devarc.bsky.social · 11mo agoLow power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks. Check - t.co/vBGGA2i0uX Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
The SCL 1.2µm PDK just dropped on eChipHub, but it's gated to students and professionals in India. verify.echiphub.in
Had fun doing bring up for XC2064, the first FPGA ever made with 64 CLBs. Scale is so small that, I was able to use Logic Cell Array editor to manually place and route the design by hand, no automation.
sovereign AI was a scam New Internet was a scam Web3 was a scam AGI by 2025 was a scam resistors are real MIM cap is real transistors are real kT/C noise is eternal Kirchhoff never lied to you parasitic capacitance will outlive your startup
Why stop at verilog gaming? Everything from sprites, controller and character animation is a state machine in itself. Now imagine putting a whole rasterization pipeline in there.
Rohan makes ASICs 🛠️@rohan-devarc.bsky.social · 4mo agoWant to play? 😋 Made with verilog.
So this one guy submitted a very cool entry for @tinytapeout.com's demoscene competition. I really liked the gradient and banner and whole starry sky implemented with LFSR. It's crazy that we can put all of this in one or two tiles.
These are bare dies of the Kintex-7 XC7K325T and its pin-compatible Chinese clone, the JFM7K325T from Fudan Micro. Only difference is that GTX transceivers of JFM7K325T behave differently, so the xilinx pcie core wouldn't work by default.
BREAKING TRUMP ANNOUNCES MAGAS WILL BECOME 10% MORE STUPID & BELOW THE AVERAGE IQ.
Fly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - github.com/aesc-silicon... @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social
Fly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - github.com/aesc-silicon... @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social
Yes, that’s a GDSII render. Yes, it’s inside Blender. Yes, it’s our design on TTSKY25A chip. @tinytapeout.com @mattvenn.net @urishaked.bsky.social
This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3 μm NMOS process with two interconnect layers. It was one of the first NMOS processes to use separate metal layers for local connections and global signals.
This looks like a matrix. Each one has 128 analog switches. We can do 8x16 analog array with one. So this is actually a analog matrix.
Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications. It has been prototyped on a Xilinx Ultrascale Plus FPGA platform. github.com/google-coral...
Leo Moser and myself will be on @crowdsupply.bsky.social 's Teardown Session talking with @helenleigh.bsky.social about @wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs
Teardown Session 56: wafer.space with Tim Ansell
YouTube video by Crowd Supply
youtu.be
FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda. He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares. www.computerhistory.org/revolution/m...
@pi0cket.bsky.social · last yr.I have been playing with the idea of a PCB inlay for the front of the case to add some flair and make the button legends a bit easier to see 😄 looks kinda nice if I do say so myself 🤣 #pi0cket #CL32 #ESP32
It was awesome to be on @chrisgammell.bsky.social 's Amp Hour podcast again. Find out more about my latest endeavor to make custom silicon manufacturing accessible and follow @wafer.space and bookmark wafer.space to keep up to date!
Chris Gammell@chrisgammell.bsky.social · 10mo agoWhat happens when one of the main providers that enables #opensource #silicon to thrive...shuts down? Companies like @mith.ro's new wafer.space jump in and offer an even more compelling option. $7K for 1000 chips on the GlobalFoundries GF180MCU process. Learn more: theamphour.com/703-building...
Low power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks. Check - t.co/vBGGA2i0uX Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.
SPI-slave device for seven-segment display on TT base board. TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.
ASICs are cool. FPGAs are ❤️. FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social @tinytapeout.com @mattvenn.net @urishaked.bsky.social
Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.
When man craves for aesthetics, he craves for God...and good quality probes.
