Hastings weather station recorded 1.2 mm of rain for the month of July.
Flux
@willflux.bsky.social
Only hardware makes it possible! FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing http://projectf.io | http://systemtalk.org
I've just realised it's one year since I first wrote about 🏝️ Isle.Computer. I believe the case for simple, open hardware is as compelling as ever. I look forward to releasing the next chapter this month. ☺️ #FPGA #OpenHardware projectf.io/isle/fpga-co...
Isle FPGA Computer
projectf.io
Pleasantly surprised to find Verilog support built in to @panic.com Nova 14. Perhaps less surprisingly, it's also 10x less memory hungry than VS Code.
It’s raining! 🌧️ It’s been so long, I’ve almost forgotten what rain is. Europe is very dry this summer.
One courgette on the allotment managed to hide amongst the leaves.
I try to learn from past hardware, but I have to wonder what Sega were thinking with the Saturn architecture. Just look at the motherboard! I don’t envy game devs starting out with it. www.copetti.org/writings/con...
🏝️ Isle.Computer is my #FPGA computer from scratch. Exciting new features have been in short supply of late due to life and spending the time I have on improving existing designs/Verilog. I'm now getting back to: * Display Device * Debug Monitor * Dynamic devices with MMIO * Codeberg migration
Just merged a signal renaming in 🏝️ Isle.Computer graphics Verilog modules. I only realised how horrible the old naming was when I took the time to review it properly. #FPGAFriday github.com/projf/isle/p...
Graphics Signal Renaming by WillGreen · Pull Request #48 · projf/isle
Naming is hard and as the graphics designs have evolved, the signal names have become increasing inconsistent and confusing. I was using the addr suffix for things that weren't addresses (the p...
github.com
Well, it works in simulation with one clock domain. But will 🏝️ Isle.Computer hardware registers work on real hardware with two clock domains? 🤔 #FPGA
I've uncovered and fixed a bug in my graphics scaling hardware. My room temperature's down 3ºC on last night. Good times.
Temperatures at Teddington Bushy Park have hit 32.8°C, provisionally equalling the all-time May record🌡️ Temperatures will continue to rise through the afternoon, we'll be giving updates here ☀️
sneak peek at Glasgow revD0 designed by Elen Eisendle / Fully Automated!
AMD (Xilinx) are no longer supporting Linux in the free version of #Vivado. You need to pay at least $1200/year! www.amd.com/en/products/... This makes no sense to me. This will make it harder for people to learn and get into #FPGA. 🤔
How to emulate an Atari YM2149 audio chip on Amiga at litteraly 0 CPU cost: arnaud-carre.github.io/2026-05-15-y... “…pure square waves sound rather bland and certainly not epic enough to accompany a future Amiga sin-dots world record.”
Playing ATARI music on Amiga for free!
How to emulate an Atari YM2149 audio chip on Amiga at litteraly 0 CPU cost, by Arnaud Carré
arnaud-carre.github.io
"The 64-bit BEAR contains the address of the last instruction that broke the sequential execution of instructions" - Why am I reading about z/Architecture? 🤔
Have you upgraded your @yosyshq.com yosys recently? #FPGA 0.49 (Jan 2025): TRELLIS_COMB: 4357 0.64 (May 2026): TRELLIS_COMB: 3682 15% LUT saving with no change in my Verilog design. 👏
Just merged 🏝️ Isle.Computer graphics refactor, fixing many small issues and general clunkiness. github.com/projf/isle/p... Working on a computer from scratch requires learning so many things in so many areas, from FPGA fanout, to Unicode, RISC-V asm, and Bresenham's line algorithm. 😅 #FPGA
Graphics Refactor 2026-05 by WillGreen · Pull Request #38 · projf/isle
Many small fixes and improvements from recent work on future Isle graphics and device designs. display_timings.v and display_modes.vh replace display.v replace hres/vres signals with params add p...
github.com
Have you upgraded your @yosyshq.com yosys recently? #FPGA 0.49 (Jan 2025): TRELLIS_COMB: 4357 0.64 (May 2026): TRELLIS_COMB: 3682 15% LUT saving with no change in my Verilog design. 👏
The TMDS clock wasn't meeting timing on #ULX3S. There is so little logic in the clk_pix_5x domain I doubted I could do much. Then I realised each channel shared a small critical ring counter. Giving each colour channel its own added 100 MHz+ to the max frequency! #FPGA 🚀 github.com/projf/isle/b...
isle/hardware/arch/ecp5/dvi_generator.v at main · projf/isle
Isle FPGA Computer. Contribute to projf/isle development by creating an account on GitHub.
github.com
Want to get your hands on a real lithography photomask? How about some silicon wafers? Enter our demoscene competition for a chance to win one! tinytapeout.com/competitions... Last 6 days to get involved! #demoscene #opensource #ASIC
Just when you thought GPU pricing had lost the ability to shock. A mobile 5070 for £1150! 😮
